Daisy II: The ALU

Adders

A half adder adds two binary digits. A full adder adds three bits.

Arithmetic logic unit

The chips built thus far have been generic, i.e. their designs are universal and would hold for any computer. The ALU is the first bit of proprietary chip added into the mix. There is no universal way of designing an ALU. It all depends on product requirements.

This ALU accepts two 16-bit inputs x and y, and six control bits and returns a 16-bit output. The control bits are as follows (in order of their precedence):

  • zx zero x-input
  • zy zero y-input
  • nx invert x-input
  • ny invert y-input
  • f function selector. 0 for x AND y1 for x + y.
  • no invert output

Additionally, the ALU computes two 1-bit outputs:

  • zr: indicates whether the ouput is zero. 1 if output = 00 otherwise.
  • ng: indicates whether the output is negative. 1 if output < 00 otherwise.

Theoretically, six control bits allow for an ALU that can perform 26 = 64 functions. The current design supports 18 functions only:

zxnxzynyfnooutput function
1010100
1111111
111010-1
001100x
110000y
001101!x
110001!y
001111-x
110011-y
011111x+1
110111y+1
001110x-1
110010y-1
000010x+y
010011x-y
000111y-x
000000x AND y (bitwise)
010101x OR y (bitwise)

Design

Multiplexers came in very handy. I was running out of space on the page so the logic for ng and zr is blackboxed in the schematic above.

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